华为HiSilicon总裁丁波 He 表示，公司工程师已提出一种新的半导体优化路径，重点不再是把更多晶体管塞进单一晶片，而是提升晶片、电路与整体系统之间的运算速度。她在上海的 IEEE 国际电路与系统研讨会上称，这一方法被命名为 Tau’s Scaling Law，并宣称将在未来数月、甚至在 2026 年冬季前展示「大幅跃进」的实证结果。

这项主张出现在美中晶片竞争与出口管制背景下：华为无法与 TSMC 合作，只能依赖使用较旧光刻设备的中芯国际（SMIC），而部分估计显示，中国在最先进制程上落后领先者超过 5 年。文章也指出，摩尔定律在数奈米尺度已逼近物理极限，Apple 等公司甚至以两颗晶片拼接来绕过单晶片扩张困难。

华为表示，其新方法可在 2031 年做出效能相当于 1.4 奈米制程的元件；相较之下，TSMC 预计将在 2028 年导入同级制程，代表中国差距可能缩小。HiSilicon 也提到 LogicFolding、奈米尺度电子效应建模、晶片协同设计与高速互连等技术，以缩短 AI 训练与推理中「资料移动」的时间，而不只是运算时间；但分析人士 Lennart Heim 认为，华为可能已接近仅靠缩小与致密化提升性能的极限，因此更倚赖 hybrid bonding 与 3D 晶片堆叠。

Huawei’s HiSilicon president Tingbo He says the company has developed a new semiconductor optimization path that shifts the focus away from packing more transistors into one chip and toward speeding computation across chips, circuits, and whole systems. Speaking at the IEEE International Symposium on Circuits and Systems in Shanghai, she named the approach Tau’s Scaling Law and said Huawei would show proof in the coming months, with a “big leap ahead” promised before winter 2026.

The claim comes amid US export controls and intense AI chip competition. Huawei cannot work with TSMC and instead depends on SMIC, which uses older lithography tools, while some estimates put China more than 5 years behind the leading edge. The article notes that Moore’s Law is hitting physical limits at nanometer scales, and that companies such as Apple already use chip stitching to bypass single-die scaling constraints.

Huawei says the new method could deliver components equivalent to a 1.4-nanometer process by 2031, versus TSMC’s expected introduction of that process in 2028. HiSilicon points to LogicFolding, nanoscale-phenomena modeling, co-design, and faster interconnects to reduce data-movement time in AI training and inference, not just compute time. But analyst Lennart Heim argues Huawei is nearing the limits of gains from shrinking and densifying chips alone, pushing it toward hybrid bonding and 3D chip stacking.